Renesas Electronics /R7FA6M4AF /SYSC /DPSBYCR

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Interpret as DPSBYCR

7 43 0 0 00 0 0 0 0 0 0 0 0 (00)DEEPCUT 0 (0)IOKEEP 0 (0)DPSBY

DPSBY=0, IOKEEP=0, DEEPCUT=00

Description

Deep Software Standby Control Register

Fields

DEEPCUT

Power-Supply Control

0 (00): Power to the standby RAM, Low-speed on-chip oscillator, AGTn (n = 0 to 3), and USBFS resume detecting unit is supplied in Deep Software Standby mode.

1 (01): Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode.

2 (10): Setting prohibited

3 (11): Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled.

IOKEEP

I/O Port Rentention

0 (0): When the Deep Software Standby mode is canceled, the I/O ports are in the reset state.

1 (1): When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode.

DPSBY

Deep Software Standby

0 (0): Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1)

1 (1): Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1)

Links

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